A typical six-transistor (6T) cell used for CMOS static random access memories (SRAM) consists of two cross-coupled CMOS inverters that store one bit of information, and two n-type FET isolation transistors on both sides of the cell that connect the cell to bitline BL and bitline complement BLN, respectively. The value of the cell is stored at one output of the inverter and the other output of the inverter is the inverse or complement of the cell value. The isolation transistors protect the value stored in the cell during precharging. The size of the isolation transistor is selected to optimize the circuit operation. A wordline control signal allows the cell to be accessed for reading or writing when needed and turns off access to the cell otherwise.
To write new data into the cell, external tristate drivers are activated to drive the bitline BL and bitline complement BLN when the wordline transistors are enabled. Since the external drivers are much larger that the small transistors used in the 6T SRAM cell, they easily override the previous state of the cross-coupled inverters. A short-circuit condition arises (for a fraction of the WL select period) when changing the information.
To read information, the wordline is activated while the external bitline drivers are switched off. Therefore, the inverters inside the SRAM cell drive the bitlines, whose value can be read-out by external logic.
The bitlines are precharged with wordline low (or off). Precharging enables the charging of both bitlines before a write or read operation. Once the proper bitline value is selected/written, the other bitline is discharged.
Current 6T SRAM cells suffer from Read mode operation instability caused by a random mismatch in threshold voltages (VTs) between adjacent transistors and devices within the cell. A dopant implant is used to set the activation threshold of the MOS transistors. The total number of dopant atoms is a function of the area under the gate of a MOS transistor. As technology scales down, the area under the gate of a MOS transistor is reduced so much so that the number of dopant atoms becomes a statistically significant variable, and can cause large random mismatches in activation threshold voltages of neighboring devices.
FIG. 1 shows a conventional 6T SRAM cell. The SRAM cell includes a first inverter comprising NFET N1 and PFET P1 with its output at storage node S1. The SRAM also includes a second inverter NFET N2 and PFET P2 with its output at storage node S2. Storage node S1 is connected to the gates of NFET N2 and PFET P2 and storage node S2 is connected to the gates of NFET N1 and PFET P1 in a cross-coupled configuration. During a READ mode operation of a conventional SRAM, the bitline (BL) and the bitline complement (BLN) are initially precharged to VDD and then set into a high impendence state. The wordline (WL) is then activated and the n-type FET isolation transistors N3 and N4 are turned on to sense the state of the respective storage nodes S1 and S2, which act to discharge either bitline BL or bitline complement BLN depending on the stored state. For example, if storage node S1 is at a low logic level and transistor N1 has an abnormally high-VT caused, for example, by random dopant implant fluctuation and isolation transistor N3 has a low VT also caused, for example, by a random dopant implant fluctuation, the charge on the bitline BL could cause storage node S1 to rise sufficiently high to flip the level at storage node S2 before its value is sensed thereby causing the circuit to fail and lose its proper state. Other combinations of threshold voltage mismatch and operating point mismatch can cause similar READ mode operation failures in a conventional SRAM. The problem with the conventional 6T SRAM cell is that during a READ mode operation, the storage nodes S1 and S2 are directly coupled to the bitline and the bitline complement, and thus are susceptible to charge sharing effects. In the case of a conventional 6T SRAM cell, allowing longer READ times will not help correct the stability problem since the bit will have already failed and lost the stored data.
In order to overcome this problem and to prevent the charge sharing effects during the READ mode operation the storage nodes are decoupled from the respective bitlines with isolation transistors. The modified cell now works in a “quasi-static” mode. During a READ mode operation the cell logic value is stored dynamically and during idle periods or when the cell is not accessed the cell logic value is stored statically as in a conventional 6T SRAM cell.